1. Field of the Invention
This invention is related to data storage buffers and more particularly to dynamic resizing of a buffer to reduce power consumption.
2. Description of the Related Art
Processors and computer systems that include the processors typically implement a virtual memory system, in which most software executing on the processors and accessing memory do so using virtual addresses. These addresses are translated through the virtual memory system to addresses (e.g., physical addresses) which are then used to access memory. Virtual memory systems offer several benefits, including: allowing software to address a larger memory space than an actual physical memory included in the system; allowing multiple independent processes to access memory while being protected from interfering with each other (e.g. by one process modifying data used by another process); etc.
Generally speaking, the virtual memory system (and particularly the mapping of virtual addresses to physical addresses) is under software control. Software builds data structures in memory that describe the virtual to physical mappings. These data structures are usually referred to as “page tables”, since many translations translate a page of the virtual address space to a page of physical memory, aligned to a page boundary in the physical memory space. Page sizes vary, from 4 kilobytes to several megabytes or even larger. A given virtual memory system often supports more than one page size.
Performing a translation frequently requires several accesses to the page tables in memory. Even if the page tables are cached, the process of searching the page table entries is a relatively lengthy process, as compared to the amount of time needed to execute a given instruction. This added latency on memory accesses (both instruction fetches and load/store operations) to perform the translation process may in turn reduce performance. Accordingly, most processors implement a cache for a subset of the translations from the page tables to speed the translation process. This cache of translations is often referred to as a translation lookaside buffer (TLB). The TLB caches the results of the translation process and typically includes an identification of the virtual address and the corresponding physical address, as well as any protection data that may be included in the virtual memory system (again, generally under the control of software). The data cached in the TLB which is used to translate a given range of virtual addresses (e.g. a page) is referred to as a “translation” for the range/page. The translation may include contents derived from multiple page table entries or one page table entry, depending on the particular virtual memory system.
TLBs typically comprise a Content Addressable Memory (CAM) and a Random Access Memory (RAM). A virtual address may be stored in an entry in the CAM, and the corresponding physical address (as well as any protection data) in a corresponding entry in the RAM. To translate a given virtual address, a portion of the virtual address corresponding to a page is compared to entries in the CAM. If a match is found, the translation data is read from the corresponding entry. When a page is not matched in the TLB (a TLB miss), the lengthy process of searching the page table entries may be performed and performance is decreased. Therefore, the TLB typically includes a large number of entries to prevent such misses. While a larger TLB may reduce the number of misses, including a larger TLB in a processor may also result in higher power consumption—due to both the large number of entries and the need to compare a relatively large number of bits (often 50-60) for each entry. While the structure of the TLB can be modified to decrease power consumption by decreasing the size of the TLB, changing the associativity of the TLB, or changing the page size, such modifications may also result in loss of performance (more TLB misses). Additionally, in a multithreaded processor, the TLB may be larger (consuming more power) in order to accommodate the multiple threads which may share the TLB. However, when only one thread is active, many of the entries in the TLB will not be used which may lead to unnecessary power consumption.